![]() Similarly it is seen that for each of the further clock pulses applied, one bit exits the PISO shift register through the output pin of n th flip-flop (Data out = Q n of FF n), which is nothing but the serial output. This is nothing but right-shift of the data stored within the register by one-bit. ![]() At this stage, if the rising edge of the clock pulse appears, then Q 1 appears at Q 2, Q 2 appears at Q 3, … and Q n-1 appears at Q n. ![]() output bit of FF 1 (Q 1) appears as the output of OR gate 1 (O 1) connected to D 2 Q 2 = output of O 2 = D 3 and so on. This causes output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF n) i.e. Next, line is driven high to activate the gates A 1 of the combinational circuits which inturn disables the gates A 2. ![]() This indicates that all the bits of the input data word are stored into the register components at the same clock tick. This causes the individual bits of the Data in to be loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B 1 which gets directly stored into FF 1 at the first clock tick). Thus the bits of the input data word (Data in) appearing as inputs to the gates A 2 are passed on as the outputs of OR gates at each individual combinational circuit.
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